module soc(
	input wire clk,
	input wire rst
);
	//CPU 指存连接线
	wire[31:0] openmips_inst_rom_inst;
	wire[31:0] openmips_inst_rom_addr;
	wire openmips_inst_rom_ce;
	//*************************
	//CPU 数存连接线
	wire openmips_ram_ce;
	wire[31:0] openmips_ram_wdata;
	wire openmips_ram_write_ce;
	wire[31:0] openmips_ram_addr;
	wire[31:0] openmips_ram_sel;
	wire[31:0] ram_openmips_rdata;
	//****************************
	//实例化MIPSCPU
	mips mips0(
		.clk(clk),
		.rst(rst),
		.inst_i(openmips_inst_rom_inst),
		.rom_ce_o(openmips_inst_rom_ce),
		.rom_addr_o(openmips_inst_rom_addr),

		.ram_rdata_i(ram_openmips_rdata), //从数据存储器读到的数据		
		.ram_ce_o(openmips_ram_ce), //数据存储器使能信号
		.ram_write_ce_o(openmips_ram_write_ce), //写使能信号
		.ram_wdata_o(openmips_ram_wdata), 
		.ram_addr_o(openmips_ram_addr),
		.ram_sel_o(openmips_ram_sel) //字节选择信号
	);
	
	//实例化指存
	inst_rom inst_rom0(
		.ce(openmips_inst_rom_ce),
		.addr(openmips_inst_rom_addr),
		.inst(openmips_inst_rom_inst)
	);
	//实例化数据存储器
	data_ram data_ram0(
		.clk(clk),
		.ram_ce(openmips_ram_ce),
		.addr(openmips_ram_addr),
		.wdata(openmips_ram_wdata),
		.write_ce(openmips_ram_write_ce),
		.sel(openmips_ram_sel), //字节选择信号
		.rdata(ram_openmips_rdata)
	);

endmodule